The Universal Debug Engine® (UDE), the modular debug, test and system analysis tool from PLS Programmierbare Logik & Systeme, now also supports the open and license-free RISC-V architecture and Intel Cyclone V SoC FPGAs. RISC-V is an instruction set architecture (ISA) based on the reduced instruction set computer (RISC) design principle. Unlike other architectures, RISC-V […]
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