The S32N55 processor, manufactured in 5 nm automotive-qualified process technology, targets central vehicle controllers that can consolidate dozens of electronic control units (ECUs) in new software-defined vehicles (SDVs). The real-time computing power of the S32N55 processor is provided by 16 Arm^® Cortex^®-R52 split-lock cores. For system management and communication, Cortex-M7 auxiliary cores complement the real-time compute. The central interconnect is based on a Network-on-Chip (NoC) that enables traffic routing across the subsystems. With hardware isolation and virtualization capabilities, the S32N55 processor is capable of supporting ISO 26262 ASIL D functional safety.

When developing software for the S32N55 processor, developers benefit, among other things, from the intuitive user interface of the UDE, which enables extremely efficient debugging and runtime analysis of applications. The Cortex-R52 main cores and the Cortex-M7 auxiliary cores are all visible and can be controlled from one common debugger user interface. This eliminates the need to open separate debugger instances for each core. The debugger user interface can be easily customized to meet specific requirements and naturally supports multiscreen operation. Freely configurable perspectives make it possible to define multiple views and switch between them to focus on a particular debugging task. Predefined configurations for the S32N55 devices also allow developers to quickly get started with their actual debug or test task without having to worry about detailed settings.

Another main multicore debugging feature of the UDE is that all cores of the S32N55 processor belong to a run control group and are synchronized for run control by default. Breakpoints and single steps work on all cores, regardless of which core hits the breakpoint or for which core the single steps are executed. This helps to keep a consistent state of the respective application during debugging.

Depending on the software partitioning of the applications running on the S32N55 processor and the particular debug scenarios, the synchronization behavior of the UDE can be changed in a flexible way. The integrated run control management of the UDE allows the user to define a run control group for partial synchronization, for example, in which only a subset of the cores is synchronized. To be able to control all cores individually, synchronization can also be deactivated completely. Especially for applications where tasks are distributed across multiple cores and shared code is used, UDE’s multicore breakpoint feature significantly eases debugging. A multicore breakpoint is effective regardless of which core is currently executing the specific code.

For particularly efficient non-invasive debugging and runtime analysis of multicore applications, the UDE also offers developers a range of useful features based on the recorded trace information from the Arm® CoreSight™ trace system, part of the S32N55 debug system. The information obtained about the program and data flow of the cores, as well as the data exchange with other components via the NoC, provides developers with a detailed insight into the runtime behavior of the system. UDE provides comprehensive analysis capabilities based on the recorded trace data. These include profiling, call graph analysis, and code coverage to verify the quality of software tests.

The Universal Access Device UAD2next with 512 MB or the UAD3+ with up to 4 GB of trace memory are available for external recording of trace data. The trace data is transferred at high speed from the chip to the UDE via a parallel trace interface. Alternatively, the trace can also be captured in an on-chip memory. In this case, the trace data is downloaded via the standard Arm® Serial Wire Debug (SWD) interface after the trace is recorded.

Easy and secure programming of the serial, quad or octal NOR flash memory of the S32N55 processors is enabled by the UDE MemTool add-on as an integral component of the UDE. eMMC and SDHC NAND memory are also supported.