The HA1200 die-level handler for the V93000 SoC test system tests singulated and/or partially assembled die. While 2.5D/3D packages enable high computing power by enabling minimum pattern length between die, stacking die can increase the risk of mixing good and bad die, leading to yield loss. Yield loss at final test, especially for 2.5D/3D packaged ICs, can cause good die, substrates, or interposers to be discarded. Equipped with Advantest’s HPC-proven ATC technology, the HA1200 enables testing powerful, high-performance SoCs with 100% test coverage. This helps reduce yield loss at final test, thus reducing loss of final multi-die assembled product.

The ATC 2kW solution for the M487x series (M4171, M4871ES and M4872) is designed to test AI/HPC IC packages at final test. The ATC 2kW solution features ultra-high-speed junction temperature (Tj) sensing and response technology to support high-performance ICs being tested at the set temperature and integrates Advantest’s unique force control technology to apply strong, stable, and safe contact to ICs with massive pin quantities. The ATC 2kW solution will support customers’ at-speed device test, enable safe 100% test coverage at final test while simultaneously increasing test quality and performance.

“Demand for AI/HPC ICs is escalating, driven by data centers, automotive, defense and other key applications,” said Kazuyuki Yamashita, Advantest senior vice president. “These ICs generate massive heat during every test process, which makes testing at full speed a challenge. We are pleased to add these new products to our portfolio to support the fast-growing AI/HPC and 2.5D/3D packaging markets.”

Advantest’s new ATC 2kW solution will be available for customer purchase in Q1 2024, and the HA1200 die-level handler will be available in Q2 2024.

To learn more about the new handler products and Advantest’s full line of automated test equipment and materials, visit us in booth 1648 at SEMICON Japan 2023, December 13-15, Tokyo Big Sight.